1 (Field of the Invention)
The present invention generally relates to a video signal processing apparatus and, more particularly, to a multiple picture reproducing apparatus designed to simultaneously reproduce a plurality of video information on a single monitor picture tube.
2 (Description of the Prior Art)
A multiple picture reproducing apparatus, hereinafter referred to as a multi-picture reproducing apparatus is well known as an apparatus capable of simultaneously reproducing a plurality of video information simultaneously on a single monitor picture tube such as, for example, a cathode ray tube, with different reproduced pictures occupying divided areas of the screen of the picture tube. As example of the prior art multi-picture reproducing apparatus is disclosed in, for example, a paper "Hitachi Mustax Digital VT-2400" published in magazine, "Terebi Gijutsu", the issue of March, 1986, p. 39-46, and a paper "VTR 4-Picture Field Memory System" (Japanese) published Dec. 10, 1986, in a Society of Television Technical Bulletin, p. 25-30, and generally takes such a construction as shown in FIG. 4 of the accompanying drawings.
Referring now to FIG. 4 for the detailed discussion of the prior art multi-picture reproducing apparatus, the apparatus comprises a demodulator for demodulating an incoming composite video signal a into a color difference signal and a Y signal; analog-to-digital (A/D) converters 1A, 1B and 1C for sampling and converting into respective digital signals the Y signal, B-Y signal and R-Y signal which are outputted from the demodulator 11; memories 4A, 4B and 4C for the storage of the respective digital signals outputted from the associated analog-to-digital converters 1A, 1B and 1C; digital-to-analog (D/A) converters for converting digital signals, read out from the respective memories 4A, 4B and 4C, into analog signals; and a modulator 12 for modulating the Y signal, the B-Y signal and the R-Y signal, all being analog signals, into a composite video signal k.
The apparatus also comprises a clock generator 6 for generating a system clock signal b synchronized with the frequency of a color burst signal included in the incoming composite video signal a; a clock control circuit 7 for generating an operating clock signal c; a sync signal separating circuit 8 for separating a horizontal synchronizing signal d and a vertical synchronizing signal e from the incoming composite video signal a; a sync signal control circuit 9 for outputting a horizontal reset signal f and a vertical reset signal g in response to the horizontal synchronizing signal d and the vertical synchronizing signal e, respectively; and a memory controller 10 operable to output a write-in control signal h and a read-out control signal i in synchronism with the operating clock signal c from the clock control circuit 7 to output and also operable in response to the horizontal reset signal f and the vertical reset signal g outputted from the sync signal control circuit 9 to generate an address signal j.
The prior art multi-picture reproducing apparatus operates in the following manner. The demodulator 11 demodulates the incoming composite video signal a into the Y signal, the B-y signal and the R-Y signal all of which are the color difference signals. The analog-to-digital converters 1A, 1B and 1C make use of the system clock signal b from the clock generating circuit 6 as a sample clock signal for converting the Y signal, the B-Y signal and the R-Y signal into the respective digital signals which are subsequently stored in the associated memories 4A, 4B and 4C in response to the write-in control signal and the address signal j both outputted from the memory controller 10 to the memories 4A, 4B and 4C. After reduced pictures have been written in the memories 4A, 4B and 4C by the operation of the memory controller 10 as will be described, the memories 4A, 4B and 4C operate in response to the read-out control signal i and the address signal j both from the memory controller 10 to reproduce the digital signals. The reproduced digital signals are then converted by the digital-to-analog converters 5A, 5B and 5C into the analog Y signal, the analog B-Y signals and the analog R-Y signal, respectively. These analog Y, B-Y and R-Y signals are subsequently modulated by the modulator 12 into the composite video signal which is in turn outputted to the monitor.
The operation of the memory controller 10 for writing the output signals from the analog-to-digital converters 1A, 1B and 1C into the respective memories 4A, 4B and 4C will now be described.
At the outset, a video signal corresponding to one picture is stored in each of the memories 4A, 4B, and 4C. At this time, the clock control circuit 7 outputs the operating clock signal c identical with the system clock signal b outputted from the clock generating circuit 6, whereas the sync signal control circuit 9 outputs the horizontal reset signal f and the vertical reset signal g at the same timings as the horizontal synchronizing signal d and the vertical synchronizing signal e, respectively. When the vertical reset signal g is applied to the memory controller 10 from the sync signal control circuit 9, the memory controller 10 initializes horizontal and vertical components (hereinafter, referred to as horizontal and vertical addresses, respectively) included in the address signal j. When the operating clock signal c is subsequently applied to the memory controller 10 from the clock control circuit 7, the memory controller circuit 10 increases the value of the horizontal address. However, when the horizontal reset signal f is applied thereto, it initializes the horizontal address and increases the value of the vertical address. Then, when the operating clock signal c is inputted to the memory controller 10, the latter outputs the write-in control signal h to write respective data in the memories 4A, 4B and 4C at appropriate address locations. However, when the vertical reset signal g is subsequently inputted to the memory controller 10, the latter ceases generating the write-in control signal h and, hence, the memory write-in operation.
Thereafter, the writing operation of reduced pictures is carried out. At this time, the clock control circuit 7 generates the operating clock signal c only at a video portion or a video signal existing region of the incoming composite video signal a, which portion can be obtained when the horizontal and vertical synchronizing signals d and e are inputted. Further, it also generates, as the operating clock signal c, a signal obtained from the system clock signal b by dividing the frequency of the latter according to the scale of reduction of the reduced pictures. Similarly, the sync signal control circuit 9 generates the horizontal reset signal f only at the video portion of the incoming composite video signal a, and also generates the horizontal reset signal f at a timing corresponding to a signal obtained from the horizontal synchronizing signal d by dividing the frequency of the latter according to the scale of reduction of the reduced pictures. The vertical reset signal g is outputtted at the timing of the vertical synchronizing signal e. When the vertical reset signal g is inputted to the memory controller 10, the memory controller 10 set both of the horizontal and vertical addresses at arbitrarily chosen addresses within a video portion. On the other hand, when the operating clock c is inputted to the memory controller 10, the horizontal address is incremented. However, when the horizontal reset signal f is inputted to the memory controller 10, the horizontal address is reset and the vertical address is incremented. When the operating clock signal c is subsequently inputted to the memory controller 10, the latter outputs the write-in control signal h to write respective data in the memories 4A, 4B and 4C at specified address locations. On the other hand, when the next succeeding reset signal g is inputted to the memory controller 10, the latter sets the horizontal and vertical addressed at other arbitrarily chosen addresses within the video portion. Thereafter, similar operation is repeated.
FIG. 5 illustrates the manner in which a plurality of, for example, four, reduced pictures are written in the memories 4A, 4B and 4C for the formation of split pictures on the screen of the picture tube. After the composite video signal corresponding to one picture has been written in all of the memories 4A, 4B and 4C as shown in FIG. 5(a), an address allocation value is set on a top left corner of the screen of the monitor picture tube. The clock control circuit 7 outputs, as the operating clock signal c, the signal obtained from the system clock signal b by dividing the frequency of the latter by two within the video portion of the incoming composite video signal a, and the sync signal control circuit 9 outputs, as the horizontal reset signal f, the signal obtained from the horizontal synchronizing signal d by dividing the frequency of the latter by two within the video portion of the incoming composite video signal a. After the write-in operation of the reduced pictures as shown in FIG. 5(b), the address allocation value is aligned with a point L lying on a vertical center line of the screen of the monitor picture tube. Thereafter, by setting the address allocation values at a point M lying at a left-hand portion of the horizontal center line of and at the center N of the screen of the monitor picture tube (as shown in FIGS. 5(c), 5(d) and 5(e), respectively, the composite video signals for four divided pictures are written in the respective memories 4A, 4B and 4C. By initializing the addresses stored in the memories 4A, 4B and 4C and subsequently reading out the data written in the memories 4A, 4B and 4C therefrom, in response to the read-out control signal i, the four divided pictures are reproduced on the screen of the picture tube (as shown in FIG. 5(e).
According to the prior art system as described above, the video signal processing apparatus is so designed as to demodulate the color difference signals from the incoming composite video signal to form the divided pictures which are subsequently modulated into the composite video signal so that video information contained in the composite video signal can be reproduced on the screen of the monitor picture tube. Not only does this render the video signal processing apparatus complicated in structure and expensive in manufacturing cost, but further the use of both the demodulator and the modulator tends to bring about a problem associated with deterioration of the color information.